1. Field of the Invention
The present invention relates to a data reproducing apparatus and, more particularly, to an apparatus for reproducing digital data, such as a digital VTR (video tape reproducer).
2. Description of the Related Art
One known example of this kind of apparatus is a digital VTR for recording and reproducing a video signal onto and from a magnetic tape in the form of a digital signal.
Such a digital VTR will be described below.
FIG. 1 is a block diagram of a reproducing system which is provided in the digital VTR.
In FIG. 1, reference numeral 101 denotes a magnetic tape. The reproducing system shown in FIG. 1 includes a recording and reproducing magnetic head 102, a head amplifier 103 for amplifying a reproduced signal supplied from the magnetic head 102, a reproduction equalizer 104 for equalizing the output from the head amplifier 103, the reproduction equalizer 104 including an LC network or the like having predetermined frequency characteristics, a data detecting circuit 105 for again converting the output from the reproduction equalizer 104 into a digital signal, which output is a signal having an amplitude which varies in analog form, a phase detector 106 for detecting a phase difference between the output from the data detecting circuit 105 and the output from an oscillator 108, and a loop filter 107 for filtering a phase error signal outputted from the phase detector 106 and feeding the resultant signal back to the oscillator 108 as negative feedback. The phase detector 106, the loop filter 107 and the oscillator 108 constitute a PLL (phase-locked loop) circuit for generating clock signals for data detection and clock signals for use in individual parts of the apparatus.
The reproducing system shown in FIG. 1 also includes a D flip-flop 110 for latching the output from the data detecting circuit 105 in accordance with a clock pulse which is the output from the oscillator 108, a demodulator 111 for digitally demodulating the data latched by the D flip-flop 110, an error-correcting decoding circuit 112 for detecting an error contained in the demodulated reproduced data and performing error correction on the data, and a reproduced signal processing circuit 113 for performing signal processing substantially opposite to that performed during recording, on the data which has been subjected to the error correction.
The operation of the reproducing system will be described below. The magnetic head 102 provides a small-level reproduced signal by tracing the magnetic tape 101 on which digital data, such as image data, is recorded, and the head amplifier 103 amplifies the small-level reproduced signal by 50-60 dB. The amplitude of the reproduced signal provided by the magnetic head 102 has the frequency characteristic shown in FIG. 2, i.e., a differential characteristic in the range of low frequencies and an attenuated characteristic due to various losses in the range of high frequencies. The reproduction equalizer 104, therefore, corrects the amplitude of the reproduced signal by using the characteristic shown in FIG. 3 which is opposite to that shown in FIG. 2. This equalization method is called integral equalization.
The data detecting circuit 105 converts the output signal from the reproduction equalizer 104 into reproduced digital data on the basis of a threshold level such as that shown in FIG. 4 by using a comparator or the like.
The phase detector 106 generates a phase error signal indicative of the phase difference between the output from the data detecting circuit 105 and the output from the oscillator 108, and the loop filter 107 performs filtering on the phase error signal and feeds back the filtered phase error signal to the control input of the oscillator 108 as negative feedback. Thus, a clock signal synchronized with the reproduced digital data is provided at the output of the oscillator 108.
The D flip-flop 110 latches the output from the data detecting circuit 105 in accordance with the clock signal, and the demodulator 111 applies digital demodulation processing based on inverse interleaved NRZI or other techniques to the digital data outputted from the D flip-flop 110. The error-correcting decoding circuit 112 performs error correction by using error-correcting parity bits added during recording, and the reproduced signal processing circuit 113 performs signal processing opposite to that performed during recording, thereby providing a reproduced video signal.
The reproduction equalizer 104 and the oscillator 108 will be described below in further detail. As shown in FIG. 3, the frequency characteristic of the reproduction equalizer 104 is not a first-order filter characteristic, such as a monotonous increase or a monotonous decrease. For this reason, in a conventional arrangement, second-order filters each consisting of a combination of an inductor L and a capacitor C are connected by buffers, as shown in FIG. 5 by way of example, whereby the characteristics of a plurality of filters each having a different cut-off frequency and a different Q (Quality Factor) are combined to realize the characteristic shown in FIG. 3.
The oscillator 108 employs a circuit construction, such as that shown in FIG. 6 by way of example. A second-order filter (resonant circuit) composed of an inductor L and a capacitor C is driven by a voltage-controlled current source 201, and the oscillator 108 oscillates at the resonant frequency of the second-order filter: ##EQU1## If a variable capacitance diode is used as the capacitor C, the oscillation frequency of the oscillator 108 can be controlled by varying the capacitance of the variable capacitance diode by using a control voltage.
A method of realizing the reproduction equalizer 104 on an integrated circuit will be described below. FIG. 7 show one example of the circuit called a gyrator that is described in "Y/C one-chip IC for video movie: AN 2400", National Technical Report, Vol. 39, No. 6, December 1993. The relationship between a current i.sub.1 which flows from a terminal A to a terminal A' and a voltage V.sub.1 across both terminals A and A'0 is expressed by the following equation: ##EQU2## where I.sub.1 and I.sub.3 represent direct currents and i.sub.1 represents an alternating current.
Thus, ##EQU3## Therefore, R (resistor) and C (capacitor) can be used to realize the inductor L on an integrated circuit. If I.sub.3 is fixed and I.sub.1 is made variable, the L value can be varied.
A method of suppressing a variation in a filter characteristic due to variations in an R value and a C value will be described below.
FIG. 8 is a block diagram showing the construction of a circuit for controlling the characteristic of a second-order filter. In the circuit shown in FIG. 8, the target cut-off frequency of the second-order low-pass filter shown by dashed lines is made equal to the oscillation frequency of a quartz-crystal oscillator 202. In this circuit, a feedback loop is formed which is arranged to vary the reference current I.sub.1 of FIG. 7 and Equation (2) so that the phase difference between a signal delayed by 90.degree. at the cut-off frequency and the output from the quartz-crystal oscillator 202 is made 90.degree., thereby adjusting an L value to obtain the target cut-off frequency.
The feature of the integrated circuit is that since the dispersion of the relative values between the individual resistors or the individual capacitors is extremely small and the inductors shown in FIG. 5 are formed by gyrators, the characteristics of the reproduction equalizer can be adjusted to appropriate characteristics by simultaneously controlling the reference currents I.sub.1 of all the gyrators.
In such a digital VTR, during a special reproduction mode such as fast forward feed and special reproduction, the speed at which a magnetic head scans magnetic tape (head relative speed) varies, so that the frequency of a reproduced signal varies.
Accordingly, if the characteristics of the reproduction equalizer are fixed, no optimum characteristics can be obtained and more errors are contained in reproduced digital data, so that a visually impaired image, such as an image containing white spots, is reproduced.
For this reason, it is necessary to control the characteristics of the reproduction equalizer and those of the PLL circuit for generating a clock signal, so that there is a need to use not only a phase detector and an oscillator which constitute the clock-generating PLL circuit, but also another group of phase detector and oscillator for adjusting the reproduction equalizer. This leads to the problem that a complicated circuit and a cost increase are needed.